RE: [sv-ac] question on clocking blocks

But what is the purpose of this restriction?  Is there a reason that it
cannot be changed? I am one of those that likes to keep related things
together, so if I define a property in my clocking block, I want to
assert it there too.

 

Lisa

 

________________________________

From: Bassam Tabbara [mailto:Bassam.Tabbara@synopsys.com] 
Sent: Friday, June 09, 2006 1:11 PM
To: Lisa Piper; sv-ac@verilog.org
Subject: RE: [sv-ac] question on clocking blocks

 

Hi Lisa,

 

It's because the clocking block is used for *declaration* only.

 

Thx.

-Bassam.

 

 

________________________________

From: owner-sv-ac@verilog.org [mailto:owner-sv-ac@verilog.org] On Behalf
Of Lisa Piper
Sent: Friday, June 09, 2006 7:18 AM
To: sv-ac@verilog.org
Subject: [sv-ac] question on clocking blocks

Why is it that concurrent_assertion_statements are not allowed in
clocking blocks?  If you can define properties and sequences in a
clocking block, then why can't you assert them too?  I think it is
better to be able to keep related components together.   I should not
need to do hierarchical referencing to assert my property or use my
sequence.

 

Lisa

 

 

 

 

clocking_declaration ::=

[ default ] clocking [ clocking_identifier ] clocking_event ;

{ clocking_item }

endclocking [ : clocking_identifier ]

 

clocking_item ::=

default default_skew ;

| clocking_direction list_of_clocking_decl_assign ;

| { attribute_instance } concurrent_assertion_item_declaration

 

concurrent_assertion_item_declaration ::=

                property_declaration

                | sequence_declaration