RE: [sv-ac] placement of "disable iff"

Hi Adam,

Probably the fair solution is to define a default reset per
module/interface, analogously to the default clocking. E.g.,

default reset !reset;

always @(posedge clk or negedge rst_n)
     begin : assert_block
     assert property (a |-> ##[1:100] b) else $error("b never came.");
     assert property (c |-> ##[1:100] d) else $error("d never came.");
end

Regards,
Dmitry

-----Original Message-----
From: owner-sv-ac@server.verilog.org
[mailto:owner-sv-ac@server.verilog.org] On Behalf Of Adam Krolnik
Sent: Thursday, June 08, 2006 6:31 PM
To: Eduard Cerny
Cc: john.havlicek@freescale.com; sv-ac@server.verilog.org
Subject: Re: [sv-ac] placement of "disable iff"



Good morning John;

You wrote:

I think we should also add a default "disable iff" at the module level
 > (and in other scopes where it makes sense) and have the default apply
 > to all the assertion directives that do not have otherwise specified
 > "disable iff" expressions.

This brings to mind a testcase I tried. The testcase is the following:


always @(posedge clk or negedge rst_n)
   if (!rst_n)
     disable assert_block;
   else
     begin : assert_block
     assert property (a |-> ##[1:100] b) else $error("b never came.");
     assert property (c |-> ##[1:100] d) else $error("d never came.");
     end


In verilog, anything executing in the block 'assert_block' would cease
to execute 
when the 'disable assert_block' statement was executed.

If the assertion statements reacted similarly to the disable statement
(equivalent
to 'disable iff (condition)' then you could have the ability to group
assertions
and disable them with one statement.

I thought of this testcase from a recommendation to place assertion
statements within
a clocked block, thereby avoiding the need to specify a clock for each
statement.

    Thanks for the consideration.

-- 
     Soli Deo Gloria
     Adam Krolnik
     ZSP Verification Mgr.
     LSI Logic Corp.
     Plano TX. 75074
     Co-author "Assertion-Based Design"