[sv-ac] A problem with local variables

There is a problem with the rules of local variables flow
when bit select is involved.

For example consider the following sequence:

sequence s1;

logic [7:0] ary;

(1, ary  = 8'b0)
##0
(
  (1, ary[val1] = 1)
    intersect
  (1,array[val2] = 2)
) ##1  ary[0] ==  2
;
endsequence

suppose that val1, val2 are signals, then this should probably be illegal
because it is possible that val1 == val2 == 0, in which case
the value of ary[0] does not flow out of the intersect expression.

Currently the LRM is not clear about this case.

A trivial solution to this problem is to requires that the indices of 
"part select"/"bit select"
of assigned local variables should be constant which are determined in 
compilation time.

I entered it as 1495 to mentis

Doron