Re: [sv-ac] coverage

Good morning Mr. Bustan;

You wrote this proposal:

   a. Overload the "disable iff" so it behaves as      before in an "assert property"
      or an "assume property", but behaves as "reject on" in a "cover property".

Accepting this will match with verilog coders current understanding of 'disable'.

   5. Whether or not to add a new directive "cover sequence".

Is this to split property coverage from sequence coverage explicitly? Are not the 
current cover statement semantics sufficient for sequences?

    Thanks.

-- 
     Soli Deo Gloria
     Adam Krolnik
     ZSP Verification Mgr.
     LSI Logic Corp.
     Plano TX. 75074
     Co-author "Assertion-Based Design"