[sv-ac] RE: [SystemVerilog Errata 0001340]: inconsistency between module ports and task arguments

 Hello Brad and all,

the problem is a limitation in the type system, this is why the
deviation existed. I added a bug note. Please have a look.

ed


> -----Original Message-----
> From: sv@eda.org [mailto:sv@eda.org] 
> Sent: Saturday, February 25, 2006 2:51 PM
> To: Eduard.Cerny@synopsys.COM
> Subject: [SystemVerilog Errata 0001340]: inconsistency 
> between module ports and task arguments
> 
> 
> On 02-25-06 11:50, bpierce <brad.pierce@synopsys.com> sent 
> you this reminder about:
> 
> http://www.eda-twiki.org/svdb/bug_view_page.php?bug_id=0001340
> 
> The fix for this issue needs to be worked on jointly with the SV-AC.
>