Re: [sv-ac] Semantics of "calling subroutines on match of a seque nce" is not well defined.

From: <vhdlcohen_at_.....>
Date: Mon Oct 31 2005 - 15:32:32 PST
 Doron,
  <First let's agree that the LRM does not answer my questions. I think 
that threads
  semantic is not defined in the LRM, and thus, different people may 
have different
 valid approaches. Do you agree? >
 Ben: Agree. but perhaps this is somehow explained in LRM language.

  < I agree that we need a different approach for sequences in 
cover/antecedent/consequent
  but I think the overall solution should be consistent, and should not 
be tool dependent. >
 Ben: Agree

 < In the second example, I think you gave a bad example. >
 Ben: Agree, I messed up. Thanks for remind me of the rule.

 < I think that for the sequence
 sequence s3;
 logic [2:0] v;
 (
 ((a ##1 a), v=1) // A subthread
 or
 ((b ##1 b), v=2) // B subthread
 ) ##1 (c, $display("c, v=%d", v));
 endsequence,

 it is clear that in an antecedent or in a cover property
 there should be two displays, one for each "thread".>
 Ben: I fail to follow the 2 displays, and the 2 threads.
  At every cycle, a new thread is started. The started thread may be in 
active state (i.e., going thru the various states), may succeeds and 
terminates, or may fail and terminate.
  Now considering a thread (let's call it THx), that thread is 
evaluating 2 subthread (my terminology, but they include The A 
subthread, and the B substhread). Note that these subthreads are within 
THx. If both subthreads succeed,what is the value of "v"? That was your 
question, and what should be displayed?
  That is ambiguous. The LRM does clarify that, nor soes it impose the 
need for 2 displays.
  Since there is only ONE common variable "v", "v" can only hold one 
value, and the subthread that modified it last wins.
 Perhaps a tool should provide a warning about such a situation.
  I don't see an easy solution. But the user should be aware that in 
situations like this, a user need to do something else.
 For example:
 logic my_a=0, my_b=0; //declaration

 sequence s3b;
 logic [2:0] v;
 (
 ((a ##1 a), v=1, my_a==1)
 or
 ((b ##1 b), v=2, my_b==1)
 ) ##1 (c, $display("c, v=%d", v));
 endsequence,

 < I think
  that this should also be the case, when the sequence is in a 
consequent,
 but I agree that currently it is a wild interpretation of the LRM. >
 Ben: True. But is this really a serious issue?
 Ben


  
Received on Mon Oct 31 15:32:45 2005

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