Re: [sv-ac] FW: Possible SV 3.1a LRM error?

Susan and Stuart,
Yes, some of the examples are in error.  Below is what I got with 
QuestaSim:
module temp;
`define true 1
logic a, b, c;
int data_out, data;

sequence rep_v;
int x;
// `true, x = 0 ##0  // compilation error
(`true, x = 0) ##0  // OK
(!a [* 0:$] ##1 a, x = x+data)[*4] ##1 b ##1 c && (data_out == x);
endsequence

endmodule : temp
The "  `true, x = 0 ##0  " is in error per LRM since there are no 
parentheses
-------------------------------------------------------------------------
-
Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
http://www.vhdlcohen.com/  ben_ f rom _abv-sva.org
* Co-Author: SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9
* Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd 
Edition, 2004, ISBN 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 
0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 
0-7923-8115
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--------

-----Original Message-----
From: Stuart Sutherland <stuart@sutherland-hdl.com>
To: sv-ac@eda.org
Sent: Fri, 9 Sep 2005 08:38:54 -0700
Subject: [sv-ac] FW: Possible SV 3.1a LRM error?


AC committee,

I received the following message regarding a possible error in some SVA
examples in the LRM.  Can someone on the AC committee please let me 
know if
this is an error?  If so, then the AC committee should keep track of 
this so
that it can be fixed at some point in time.

Stu
~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland
stuart@sutherland-hdl.com
+1-503-692-0898

-----Original Message-----
From: Susan Sien [mailto:Susan.Sien@synopsys.com]
Sent: Thursday, September 01, 2005 9:45 AM
To: info@sutherland-hdl.com
Subject: For Stuart's attn on possible SV 3.1a LRM error?
Importance: High

Hi Stuart,

In the LRM, on page 225 (pdf page 241) it says for local variable
assignments:

"The variable can be assigned at the end point of any syntactic
subsequence
by placing the subsequence, comma separated from the sampling
assignment, in parentheses."

But some of the subsequent examples don't have the parenthesis, for
instance
some on the bottom of the same page on the following page.

I used VCS on the example shown on page 226 for sub_seq2 and got a parse
error.  So I'm wondering if the LRM has some mistakes or if the VCS
parser is incorrect.

Thanks.

Susan Sien
Synopsys
2321 Rosecrans #3200
El Segundo, CA 90245
310 725 2310