RE: [sv-ac] Ballot item 241 proposal

Hi Ed/Surrendra/Bassam,

Baed on these emails, I am assuming that no modifications
are needed in the proposal. If anyone disagrees, please let
me know.

Thanks.
Manisha

-----Original Message-----
From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of
Eduard Cerny
Sent: Monday, April 18, 2005 10:02 AM
To: Surrendra.Dudani@synopsys.com; sv-ac@eda.org
Subject: RE: [sv-ac] Ballot item 241 proposal

I agree.
ed 

> -----Original Message-----
> From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of 
> Surrendra Dudani
> Sent: Monday, April 18, 2005 12:56 PM
> To: sv-ac@eda.org
> Subject: RE: [sv-ac] Ballot item 241 proposal
> 
> 
> Hi Manisha,Ed,Bassam:
> I think the example below that Ed pointed out is not a problem. Since 
> ck.a is already sampled (prepone region), the value ck.a in the 
> assertion without sampling at clk2 vs. re-sampling at clk2 should be 
> the same. Multiple sampling of the same variable become redundant in 
> the prepone region. The important thing to note is that the value of 
> ck.a is stable throughout any time unit and doesnot change by any 
> other clock sampling. It also matches with the proposal wording "The 
> assertion using the clocking block variable shall not do its own 
> sampling on the variable, but rather use the sampled value produced by

> the clocking block."
> 
> In the interest of time, I suggest not to add this example in the 
> proposal.
> 
>  clocking ck @(posedge clk);
>   input a;
> endclocking
> 
> property p4;
>   @(posedge clk2) ck.a;
> endproperty
> 
> a5: assert property(p4);
> 
> 
> Surrendra
> -----Original Message-----
> From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of 
> Eduard Cerny
> Sent: Saturday, April 16, 2005 6:11 PM
> To: Surrendra.Dudani@synopsys.COM; sv-ac@eda.org
> Subject: RE: [sv-ac] Ballot item 241 proposal
> 
> Hi,
> 
> I wonder if the examples in Mantis #626 (issue 241) should also 
> include the following situation:
> 
> clocking ck @(posedge clk);
>   input a;
> endclocking
> 
> property p3;
>   @ck ck.a;
> endproperty
> 
> a5: assert property(p3);
> 
> This would be the case of possible double sampling too and it should 
> state again that the results is the same as in the other cases a1-a4. 
> Or is this illegal?
> 
> And an example of the illegal case:
> 
> clocking ck @(posedge clk);
>   input #1 a;
> endclocking
> 
> property illegal_sampling;
>   @ck ck.a;
> endproperty
> 
> a5: assert property(illegal_sampling);
> 
> -----------
> And what about the following case? Is it legal? If we go by the timing

> diagram in the proposal, this would mean resampling the sampled value 
> by posedge clk by the posedge of clk2:
> 
> clocking ck @(posedge clk);
>   input a;
> endclocking
> 
> property p4;
>   @(posedge clk2) ck.a;
> endproperty
> 
> a5: assert property(p4);
> 
> ----------
> 
> ed
> 
> 
> 
> > -----Original Message-----
> > From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of 
> > Surrendra Dudani
> > Sent: Thursday, April 14, 2005 8:58 PM
> > To: sv-ac@eda.org
> > Subject: [sv-ac] Ballot item 241 proposal
> > 
> > 
> > Please review ballot issue 241 with Manisha's proposal in
> mantis item
> > #626.
> > If I don't hear anything by tomorrow, I'll assume it's ok to change 
> > the status to resolve.
> > Surrendra
> > ****************************************
> > Surrendra A. Dudani
> > Synopsys, Inc.
> > 377 Simarano Drive, Suite 300
> > Marlboro, MA 01752
> > 
> > Tel:   508-263-8072
> > Fax:   508-263-8123
> > email: Surrendra.Dudani@synopsys.com
> > ****************************************
> > 
> > 
> > 
> 
> 
> 
> 
> 
>