[sv-ac] P1800 issues - STU2

Hello everyone,

I spent some time to look into the issue of variable declaration
before use issue and here is what I found. Although Verilog 1364 
LRM allows usage of variables in functions/tasks before their 
declaration but it does not work in Modelsim. 
Here is an example which I tried:

module A;
function integer abc(input i);
begin
if (a)
  abc = 1;
else
  abc = 0;
end
endfunction

reg a;
endmodule

Based on some discussion with others, looks like it is not supported
in some other standard simulators either. 

However if I change the example to use hierarchical reference (A.a),
it works fine. 

It will be good if some other people try it with other simulators 
and let us know. If it works fine in other simulators, I am fine
with this proposed change.

Thanks.
Manisha

Clause 18 on assertions is ambiguous as to whether identifiers
must be declared prior to being referenced in a property or sequence
block.
Some existing implementations require the declaration come first, and
some
do not.  It is my understanding that Verilog allows identifiers to be
referenced prior to declaration in specify blocks, tasks, and functions.
If
this is correct, then it would be reasonable for users to expect that
property and sequence blocks be consistent with that rule.  Allowing
reference before declaration might also help with binding externally
declared properties and sequences to a design block.  In either case,
the
P1800 LRM should explicitly state the rule of order for declaration
versus
reference in a property or sequence block.  The current ambiguity has
lead
to code that is not portable across multiple tools. suggested_remedy =