Did the initialization of property and sequence local vairable ever make into the spec? e.g., property P; int i=0; int j; a |=> (!b, i +=1)[*0:255] ##1 c && addr[0:7]=i; endproperty : P Ben -------------------------------------------------------------------------- Ben Cohen Trainer, Consultant, Publisher (310) 721-4830 http://www.vhdlcohen.com/ ben_ f rom _abv-sva.org * Co-Author: SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9 * Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0 * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 * Component Design by Example ", 2001 isbn 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115 --------------------------------------------------------------------------------- -Received on Wed Mar 30 12:28:49 2005
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