[sv-ac] SVA: Intialization of local variables in properties and sequences

As addressed previously, I would like to see the capability to initialize local variables in properties and sequence declarations.   The initializations must be STATIC. 
This would bring it in line with other initialization of variables in the code, and would simplify coding.  For example: 
property P (a, b, c); 
 int v_a=a; // actual argument for "a" MUST be STATIC
 int v_b=0; // initialized, but value not used in this example
   @ (posedge clk) (b, v_b=b, v_a+=1) [* 0:10] 
      ##1 c; 
endproperty : P
assert property (P(5, m, n));

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Ben Cohen Trainer, Consultant, Publisher (310) 721-4830 
http://www.vhdlcohen.com/  ben_ f rom _abv-sva.org
* Co-Author: SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9
* Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0 
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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