[sv-ac] Two new issues filed

Hi, all,

I have filed two new issues in the SVDB at the request of Atrenta:

http://www.eda-twiki.org/svdb/bug_view_page.php?bug_id=0000380
http://www.eda-twiki.org/svdb/bug_view_page.php?bug_id=0000381

The body of the two issues is:

1. Section 17.7.10 and 17.12.5 of the LRM refers to using "ended" and "matched" with sequences. But both of them do not appear anywhere in the BNF, and are not even System Verilog keywords.

2. Following example as mentioned in Section 17.8 of LRM sequence data_check; int x; a ##1 !a, x = data_in ##1 !b[*0:$] ##1 b && (data_out == x); endsequence cannot be parsed by the current BNF. The BNF mentions sequence_expr : ( expression_or_dist {, sequence_match_item } ) [ boolean_abbrev ] | ( sequence_expr {, sequence_match_item } ) [ sequence_abbrev ] so the example should be sequence data_check; int x; a ##1 (!a, x = data_in) ##1 !b[*0:$] ##1 b && (data_out == x); endsequence

I'd appreciate it if someone could take a look and comment in the SVDB.

Thanks,

Karen
Received on Fri Feb 11 16:33:16 2005