Re: [sv-ac] 1800 draft 3 review

Review Comments:
Grammatical error in 17.6.1
Change
from:
"A formal argument which is not prefixed by a type will be untyped."

TO:
"A formal argument that is not prefixed by a type will be untyped."

---
FROM:
"The supported data types for sequence formal arguments are the types which are allowed for operands in assertion expressions"
TO:
"The supported data types for sequence formal arguments are the types allowed for operands in assertion expressions"
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I am having a problem understanding the example: 
sequence foo(bit a, bit b);
  bit loc_a;
   (1'b1, loc_a=a) ##0 
   (t == loc_a) *[0:$] ##1 b
endsequence
First, the syntax is wrong, and it should be: 
   (1'b1, loc_a=a) ##0 
   (t == loc_a) [*0:$] ##1 b; 
2nd, what will the value of loc_a be in the frist cycle of the sequence? 1'b0 or "a"?
The assignment of loc_a is in the SAME cycle the comparison of the variable is made to "t".
I would guess that the sampled value of loc_a at the first cycle the sequence is evaluated is 
the default for the type, or 1'b0 in this case.  
Perhaps the following might make things clearer: 
sequence foo(bit a, bit b);
  bit loc_a=1'b0;
   (1'b1, loc_a=a) ##0 
   (t == loc_a) *[0:$] ##1 b
endsequence
---------------
  
17.11.1  Same comments on the misuse of the word "which" as those made for the sequence (17.6.1)/
 
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17.12.6
From" It shall be considered an error to invoke this method on sequences which treat their formal ...
TO" It shall be considered an error to invoke this method on sequences that treat their formal ...
From: A sequence treats its formal argument as a local variable if the formal argument is used as an 1value in ..
"1value"?? "lvalue"?  You meas  "as a value in operator_asignment..."
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17.14
Item "5) A multiply-clocked sequence ..."
I never liked the term "mulitply-clock" as multiply implies to me some artihmetic operator or a multiple of something.  
I prefer the term "multi-clock", inferring several clocks. 
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Ben Cohen Trainer, Consultant, Publisher (310) 721-4830 
http://www.vhdlcohen.com/ vhdlcohen@aol.com 
Author of following textbooks: 
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004 isbn 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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