RE: [sv-ac] Fixed final proposal for 196 uploaded

Hi Hillel,
 
The text in the Documentation section seems contradictory: alll data types
supported and then they are retsricted to 17.4.1?
 
ed
 
 
Documentation:
 
Formal parameters of properties and sequences can optionally be typed. All
SystemVerilog data types are supported. To
declare a type for a formal parameter of a property or sequence it is
required to prefix the parameter with a type. A formal
parameter which is not prefixed by a type will be untyped. See above for the
definition of untyped variables.
 
Exporting values of local variables thru typed formal parameters is not
supported.
 
The supported data types for properties and sequence formal paramaeters are
the same as specfied in section 17.4.1.

  _____

From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of Miller
Hillel-R53776
Sent: Monday, November 22, 2004 1:01 PM
To: Miller Hillel-R53776; 'sv-ac@eda.org'
Subject: [sv-ac] Fixed final proposal for 196 uploaded

Proposal for adding datatypes to formal parameters of assertion sequences
and properties
 

Motivation
----------
1. To be aligned with the overall System Verilog data typing definitions.
System Verilog is
   a strongly typed langauge.
2. To allow strongly typed code to provide better compiler/tool
compabilities, optimization and
   error detection.
3. To extend the data types that can be passed to assertions. One may pass
an class object
   and activate a method of that class.
4. To allow activations of properties thru the DPI, with correct data types.
5. To allow a well defined interface to properties such that external users
do
   not pass arguments that provide undesirable behavior.
 
Syntax Changes
--------------
 
Note: The following changes make usage of already defined BNF for
'tf_port_list' and 'list_of_arguments'.
 
We simplify tf_port_list for the sake of explanation of what parts we steal
and what
we do not steal from the existing syntax in order to add the optional data
types.
No changes in the tf_port_list BNF is required.
 
tf_port_list ::=
  tf_port_item { , tf_port_item }
 
tf_port_item ::=
  [data_type] port_identifier variable_dimension [ = expression ] ;
 
data_type ::=
integer_vector_type [ signing ] { packed_dimension }
| integer_atom_type [ signing ]
| struct_union [ packed [ signing ] ] { struct_union_member {
struct_union_member } }
{ packed_dimension }
| enum [ enum_base_type ] { enum_name_declaration { , enum_name_declaration
} }
| type_identifier { packed_dimension }
 

What is supported?
------------------
1. pass by reference as default - a typed formal parameter which is a pass
by reference parameter, will get the value of the
respective evaluation of the actual parameter at the time the formal
parameter is referenced. This is what is supported
today with untyped types.
2. Backward compatibility with the current formal parameter definition.
Allowing untyped formal parameters.
3. Default parameters are supported.
4. Example of types that are supported are:
 
typedef int [4] array;
typedef struct { int a, b, c,d } record;
union { record r; array a; } p, q;
 
What is not supported?
----------------------
1. Assigning from within a property/sequence to a typed formal parameters.
A typed formal
parameter can not be used as a local variable.
 
The following example is not allowed:
 
sequence sub_seq2(bit lv);
a ##1 !a, lv = data_in ##1 !b[*0:$] ##1 b && (data_out == lv);
endsequence
 
sequence seq2;
int v1;
c ##1 sub_seq2(v1) ##1 (do1 == v1); // v1 is now bound to lv
endsequence
 

2. input/output/inout direction to parameters with datatypes.
3. 'pass by value' formal parameters.
4. Declaring a list of formal parameters with a specific type. Each formal
parameter will require a prefix
   which specifies its declared data type. Any formal parameter that is not
prefixed by a type will be untyped no
   matter where appears in the port list.
5. The following types are not supported:
 
- non-integer types (shortreal, real and realtime)
- string
- event
- chandle
- class
- associative arrays
- dynamic arrays
- Anonymous struct, union or enumerations. The type matching rules do not
allow independent
anonymous declarations to match. For example the following is not allowed
 
struct packed { logic f1 } var_a;
property simple_prop(
   struct packed { logic f1} param_1;
   )
  ...
endproperty
assert simple_prop(var_a); // This is a type casting/matching error.
 
(1) Property declaration
 
Change:
 
property_declaration ::=
  property property_identifier [ ( [ list_of_formals ] ) ] ;
  { assertion_variable_declaration }
  property_spec ;
endproperty [ : property_identifier ]
 
To:
 
property_declaration ::=
  property property_identifier [ ( [ tf_port_list ] ) ] ;
  { assertion_variable_declaration }
  property_spec ;
endproperty [ : property_identifier ]
 
(2) Property instance
 
Change:
 
property_instance ::=
ps_property_identifier [ ( [ actual_arg_list ] ) ]
 
To:
 
property_instance ::=
ps_property_identifier [ ( [ list_of_arguments ] ) ]
 
(3) Sequence declaration
 
Change:
 
sequence sequence_identifier [ ( [ list_of_formals ] ) ] ;
{ assertion_variable_declaration }
sequence_expr ;
endsequence [ : sequence_identifier ]
 
To:
 
sequence sequence_identifier [ ( [ tf_port_list ] ) ] ;
{ assertion_variable_declaration }
sequence_expr ;
endsequence [ : sequence_identifier ]
 
(4) Sequence instance
 
Change:
 
sequence_instance ::=
ps_sequence_identifier [ ( [ actual_arg_list ] ) ]
 
To:
 

sequence_instance ::=
ps_sequence_identifier [ ( [ list_of_arguments ] ) ]
 
Documentation:
 
Formal parameters of properties and sequences can optionally be typed. All
SystemVerilog data types are supported. To
declare a type for a formal parameter of a property or sequence it is
required to prefix the parameter with a type. A formal
parameter which is not prefixed by a type will be untyped. See above for the
definition of untyped variables.
 
Exporting values of local variables thru typed formal parameters is not
supported.
 
The supported data types for properties and sequence formal paramaeters are
the same as specfied in section 17.4.1.
 
 
Examples:
 
1. Two equivalent ways of passing parameters, the first has untyped
parameters and the second has typed parameters:
 
property rule6_with_no_type(x, y);
##1 x |-> ##[2:10] y;
endproperty
 
property rule6_with_type(bit x, bit y);
##1 x |-> ##[2:10] y;
endproperty
 
2. Example where a local variable is used to sample a formal parameter, in
order to get the effect of
   pass by value. This is needed because currently pass-by-value is not
supported.
 
sequence foo(bit a, bit b);
bit loc_a;
(1'b1, loc_a = a) ##0
(t == loc_a)*[0:$] ##1 b
endsequence
 
 
Received on Mon Nov 22 10:28:16 2004