Re: [sv-ac] AC 196:

Hi Manisha, Hillel:

There was a lot of effort to achieve semantic alignment
between PSL and SVA, but we did not achieve full syntactic
alignment because of overriding considerations of integrity
of each of the languages individually.

I think that in moving forward, we should never allow
arbitrary divergence, and we should try our best to maintain
alignment when making modifications to SVA.

PSL already has argument types, but PSL does not have local
variables. Therefore, PSL is not set up to do pass by value
of HDL expressions. PSL does have special types for sequences
and properties (SEREs and formulas) and for compile-time integer
constants. My understanding is that all PSL arguments are passed
by reference except the compile-time integer constants, which are
passed by value.

I think that due consideration should be given to the fact that
default pass by reference of typed arguments in SVA is better
in alignment with PSL than default pass by value.

Best regards,

John H.

>
> Hi Hillel,
>
> I can understand that you are an SVA fan. But there are
> lot of people who use both the languages and it is
> important to try to keep both the languages as aligned as
> possible.
>
> Thanks.
> Manisha
>
> -----Original Message-----
> From: Miller Hillel-R53776 [mailto:r53776@freescale.com]
> Sent: Friday, November 19, 2004 12:20 AM
> To: Kulshrestha, Manisha; sv-ac@eda.org
> Subject: RE: [sv-ac] AC 196:
>
> Manisha,
>
> SVA is part of SystemVerilog. It is much more important that SVA is
> consistent with SV over SVA being consistent with PSL. As an SVA fan
> making it more consistent with SV is a differentiating factor to the
> advantage of SVA.
>
> Regards
> Hillel
>
> -----Original Message-----
> From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org]On Behalf Of
> Kulshrestha, Manisha
> Sent: Wednesday, November 17, 2004 10:32 PM
> To: sv-ac@eda.org
> Subject: RE: [sv-ac] AC 196:
>
>
> Hi Hillel,
>
> I like the idea of adding types to the properties. But this issue of
> passing by value vs. reference seems to be a complete new way of looking
> at properties. Also, passing by value makes it inconsistent from psl.
>
> Manisha
>
> -----Original Message-----
> From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of Adam
> Krolnik
> Sent: Wednesday, November 17, 2004 11:52 AM
> To: Miller Hillel-R53776; sv-ac@eda.org
> Subject: Re: [sv-ac] AC 196:
>
>
>
> Hi Hillel;
>
> You wrote:
>
> >Justification of both capabilities is based on the fact that most
> popular languages >support both >types of parameters. This includes
> SystemVerilog.
>
> What I was thinking for justification a set of properties/sequences is
> provided that you wish to write and why the pass-by-value functionality
> should be included.
>
>
> You wrote:
>
> >For pass by value, this:
> > reg val1, val2;
> > ... (val1 = parameter_a, val2 = parameter_b,
> property_rule6(val1, val2)) ...
> >becomes, this:
> > ... property_rule6(parameter_a, parameter_b) ...
> >which is already simpler. It also may execute faster.
>
> However, IMHO, the most common cases of properties and sequences would
> be:
>
> property my_simple_property_with_arguments(valid, datum) ...
>
> This would have an error prone declaration if one chooses to formally
> declare the types of the arguments (hoping to provide a safety and
> documentation to the
> user.)
>
> property my_simple_property_with_arguments(
> ref reg valid, // must be ref...
> ref reg datum // must be ref...
> );
> ...
>
> Should the user forget to add the 'ref' keyword, they obtain a most
> likely invalid property.
>
> property my_simple_property_with_arguments(
> reg valid, // Whoops! only one value now!
> reg datum // Whoops! only one value now!
> );
> ...
>
> There has not been confusion on the model of sequences and properties
> being module like or task call like before. I fear choosing a task call
> like model provides a more dangerous syntax and little overall benefit.
> This model we speak of does not even impact the implementation of
> sequences and properties. Thus I would ask that consideration be given
> to ease of use, when choosing a conceptual model to explain a
> specification from.
>
> Thanks.
>
> Adam Krolnik
> Verification Mgr.
> LSI Logic Corp.
> Plano TX. 75074
> Co-author "Assertion-Based Design"
>
>
>
>
>
Received on Fri Nov 19 16:45:33 2004