RE: [sv-ac] AC 196:

Ed,

Where did john mention this, I never found it? What do you mean by preponed region?
I am not sure I follow your question.

Sampling becomes optional and is not required before activating the sequence
when passing by value.

Regards
Hillel

-----Original Message-----
From: Eduard Cerny [mailto:Eduard.Cerny@synopsys.com]
Sent: Wednesday, November 17, 2004 3:16 PM
To: Miller Hillel-R53776; 'Adam Krolnik'
Cc: Eduard.Cerny@synopsys.com; sv-ac@eda.org
Subject: RE: [sv-ac] AC 196:

Hi Hillel,

If I understand it right, then effectively passing by value would remove the
sampling in preponed region (is it what we want?). But, as John also
mentioned, I am not clear on when the values are taken from the variable
passed through that kind of argument.

ed
 

> -----Original Message-----
> From: Miller Hillel-R53776 [mailto:r53776@freescale.com]
> Sent: Wednesday, November 17, 2004 6:13 AM
> To: 'Adam Krolnik'
> Cc: Eduard.Cerny@synopsys.COM; sv-ac@eda.org; Miller Hillel-R53776
> Subject: RE: [sv-ac] AC 196:
>
> Adam,
>
> Your examples are correct.
>
> I prefer the form of a task because you have a definition of
> 'pass by value' and 'pass by reference'. I believe that both
> of these are needed. With modules I just have pass by
> reference. The 'pass by value' saves the need of sampling and
> then calling the sequence.
>
> Thanks
> Hillel
>
> -----Original Message-----
> From: Adam Krolnik [mailto:krolnik@lsil.com]
> Sent: Tuesday, November 16, 2004 10:39 PM
> To: Miller Hillel-R53776
> Cc: Eduard.Cerny@synopsys.com; sv-ac@eda.org
> Subject: Re: [sv-ac] AC 196:
>
>
>
>
> Hi Hillel, Eduard;
>
> So as a comparative set of properties, these are the
> equivalent forms, correct?
>
>
> property rule6_with_no_type(x, y);
> ##1 x |-> ##[2:10] y;
> endproperty
>
> property rule6_with_type(ref bit x, ref bit y);
> ##1 x |-> ##[2:10] y;
> endproperty
>
>
> And these are definitely not the same...
>
> property rule6_with_no_type(x, y);
> ##1 x |-> ##[2:10] y;
> endproperty
>
> property rule6_wrong_type(bit x, bit y);
> ##1 x |-> ##[2:10] y;
> endproperty
>
>
> I would have though the model was that of a module, not a
> model of a task (call or
> invocation.) With a model of a module, then ports would not
> need the 'ref' keyword to be able to monitor the (possibly)
> changing (in time) value of expressions.
>
>
> Thanks.
>
> Adam Krolnik
> Verification Mgr.
> LSI Logic Corp.
> Plano TX. 75074
> Co-author "Assertion-Based Design"
>
Received on Wed Nov 17 05:29:11 2004