RE: [sv-ac] RE: AC 296

I thought that we agreed that triggered would not be allowed in sequences.
But then neither would $past on it. But I do not see why not to use
$past(qT.ended) in a sequence instead. Also, the sequences to which ended is
applied must have a clock.

Ed
 

> -----Original Message-----
> From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On
> Behalf Of VhdlCohen@aol.com
> Sent: Friday, November 12, 2004 1:39 PM
> To: Adam Krolnik; "Kulshrestha, Manisha"
> Cc: sv-ac@eda.org
> Subject: Re: [sv-ac] RE: AC 296
>
> I would like to add the following is also legal:
> That was not clear in the LRM.
> $past(sequence_instance.triggered)
> For example, ALL LEGAL:
> // sequence a then b
> sequence qT; a ##1 b; endsequence : qT
>
> // sequence a then b then don't care
> sequence qTended; a ##1 b ##1 `true; endsequence : qTended
>
> // property example:
> property P1; @ (posedge clk) k |-> $past(qT. triggered);
> endproperty : P1 property P2; @ (posedge clk) k |->
> qTended.ended; endproperty : P2
>
> Ben Cohen
>
>
> In a message dated 11/12/2004 12:17:22 PM Eastern Standard
> Time, Adam Krolnik <krolnik@lsil.com> writes:
>
> >
> >
> >Good morning all;
> >
> >It may be best to provide a table listing the legal contexts
> for each
> >of the methods in question (.ended, .matched, .triggered)
> and any others if necessary.
> >
> >There is a fine line between .ended and .triggered and users will
> >appreciate a summary of the legal contextx for each.
> >
> >contexts include:
> >
> > wait / @()
> > sequences/properties
> > disable
> > argument to sequence/property
> > local variable rhs
> >
> >
> >others?
> >
> >
> >
> > Adam Krolnik
> > Verification Mgr.
> > LSI Logic Corp.
> > Plano TX. 75074
> > Co-author "Assertion-Based Design"
> >
> --------------------------------------------------------------
> ---------------
> Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
> http://www.vhdlcohen.com/ vhdlcohen@aol.com Co-author /
> author of following textbooks:
> * SystemVerilog Assertions Handbook, ISBN 0-9705394-7-9, Dec'04
> * Using PSL/SUGAR for Formal and Dynamic Verification 2nd
> Edition, 2004 isbn 0-9705394-6-0
> * Real Chip Design and Verification Using Verilog and VHDL,
> 2002 isbn 0-9705394-2-8
> * Component Design by Example ", 2001 isbn 0-9705394-0-1
> * VHDL Coding Styles and Methodologies, 2nd Edition, 1999
> isbn 0-7923-8474-1
> * VHDL Answers to Frequently Asked Questions, 2nd Edition,
> isbn 0-7923-8115
> --------------------------------------------------------------
> ----------------
>
Received on Fri Nov 12 11:19:37 2004