RE: [sv-ac] SVA: What is the defintion of "identical clock"?

I second the need for a defintion in the LRM.
Many LRMs do contain a separate section for defintion of terms. This one does not.
In any case, the term "identical" is ambiguous.
Ben

In a message dated 10/27/2004 1:36:09 PM Eastern Daylight Time, "Stuart Sutherland" <stuart@sutherland-hdl.com> writes:

>So what does "syntactically identical" mean? To me, from a user's
>perspective, that is just as ambiguous as the original wording. I still
>have no idea what is required when assertions refer to "identical clocks".
>The LRM needs to define this term with total clarity for both implementers
>and users.
>
>Stu
>~~~~~~~~~~~~~~~~~~~~~~~~~
>Stuart Sutherland
>stuart@sutherland-hdl.com
>+1-503-692-0898
>
>
>> -----Original Message-----
>> From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On
>> Behalf Of Eduard Cerny
>> Sent: Wednesday, October 27, 2004 8:12 AM
>> To: VhdlCohen@aol.com; sv-ac@eda.org
>> Cc: stuart@sutherland-hdl.com; cliffc@sunburst-design.com
>> Subject: RE: [sv-ac] SVA: What is the defintion of "identical clock"?
>>
>> Defining semantic identity could be quite tricky. Perhaps we
>> could just state that the clocks should be syntactically
>> identical. The tools can do better if so desired.
>>
>> ed
>>
>>
>> > -----Original Message-----
>> > From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org]On Behalf Of
>> > VhdlCohen@aol.com
>> > Sent: Tuesday, October 26, 2004 8:39 PM
>> > To: sv-ac@eda.org
>> > Cc: stuart@sutherland-hdl.com; cliffc@sunburst-design.com
>> > Subject: [sv-ac] SVA: What is the defintion of "identical clock"?
>> >
>> >
>> > The LRM discusses at great length the issue of "identical" or
>> > "non-identical" clocks, but the LRM fails anywhere to
>> define what is
>> > an "identical clock". LRM Std P1364 also fails to define identical.
>> > Specifically, Identical in what way? The exact same signal?
>> The same
>> > period? Identical in some other way? Is clk1 aliased to clk2
>> > identical? Are signals connected via a module port so that they are
>> > the same signal? Does "assign clk1=clk2;" create identical clocks?
>> >
>> > Below is a typical reference in the LRM to identical clocks.
>> > LRM 17.12.1 Multiply-clocked sequences states the following:
>> > "
>> > @(posedge clk0) sig0 ##1 @(posedge clk1) sig1 ....
>> > If clk0 and clk1 are identical, then the clocking event does not
>> > change after ##1 and the above sequence is equivalent to the
>> > singly-clocked sequence @(posedge clk0) sig0 ##1 sig1
>> >
>> > Thanks,
>> > Ben Cohen
>> > --
>> >
>>
>>
>>
>
>
>

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Ben Cohen Trainer, Consultant, Publisher (310) 721-4830 
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Author of following textbooks: 
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004 isbn 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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