RE: [sv-ac] SVA: What is the defintion of "identical clock"?

Defining semantic identity could be quite tricky. Perhaps we could just
state that the clocks should be syntactically identical. The tools can do
better if so desired.

ed

> -----Original Message-----
> From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org]On Behalf Of
> VhdlCohen@aol.com
> Sent: Tuesday, October 26, 2004 8:39 PM
> To: sv-ac@eda.org
> Cc: stuart@sutherland-hdl.com; cliffc@sunburst-design.com
> Subject: [sv-ac] SVA: What is the defintion of "identical clock"?
>
>
> The LRM discusses at great length the issue of "identical" or
> "non-identical" clocks, but the LRM fails anywhere to define what
> is an "identical clock". LRM Std P1364 also fails to define identical.
> Specifically, Identical in what way? The exact same signal? The
> same period? Identical in some other way? Is clk1 aliased to clk2
> identical? Are signals connected via a module port so that they
> are the same signal? Does "assign clk1=clk2;" create identical clocks?
>
> Below is a typical reference in the LRM to identical clocks.
> LRM 17.12.1 Multiply-clocked sequences states the following:
> "
> @(posedge clk0) sig0 ##1 @(posedge clk1) sig1
> ....
> If clk0 and clk1 are identical, then the clocking event does not
> change after ##1 and the above sequence is equivalent to the
> singly-clocked sequence
> @(posedge clk0) sig0 ##1 sig1
>
> Thanks,
> Ben Cohen
> --
>
Received on Wed Oct 27 08:12:16 2004