RE: [sv-ac] Uploaded proposal for eratta 196 - Also attached

Adam,

Thanks, hope it will be accepted.

In CBV we found that what you are asking for was best implemented using a template layer. I recall Intel taking this approach as well and if I am
not mistaken Synopsys proposed templates as well. This is a different proposal and of course it is required.

Best Regards
Hillel

-----Original Message-----
From: Adam Krolnik [mailto:krolnik@lsil.com]
Sent: Friday, October 08, 2004 4:48 PM
To: Miller Hillel-R53776
Cc: Eduard.Cerny@synopsys.com; sv-ac@eda.org
Subject: Re: [sv-ac] Uploaded proposal for eratta 196 - Also attached

Good morning Hillel;

I like the proposal you have made.

Have you considered inclusion of the ability to pass sequences or properties as
arguments to another sequence or property? Others have asked of this capability.
One should also consider passing of properties and sequences through module/interface
ports as the capability is very similar in nature.

Lastly, how can we provide for parametric data sizes? Do we use type passing to achieve
this, instead of the previous parameter redefinition?

E.g

For modules with variable data size, we write:

module #(
          parameter WIDTH = 2
          ) queue(
   input [WIDTH-1:0] data_in;
   ...
   );

What do we do for properties?

property correct_value(logic req,
                        logic ack
                        reg [31:0] good_data
                        ...
    reg [31:0] returned_data;
    ...

What should I do to make the value 31 parametric and allow for larger data size, like I
am capable of doing in modules today?

     Adam Krolnik
     Verification Mgr.
     LSI Logic Corp.
     Plano TX. 75074
     Co-author "Assertion-Based Design"
Received on Fri Oct 8 08:12:50 2004