Accellera SuperVerilog Assertion Activity: Re: [sv-ac] SVA: LRM

From: John Havlicek <john.havlicek@motorola.com>
Date: Mon May 03 2004 - 08:48:39 PDT

Hi Surrendra:

I think Hillel pointed out these missing parentheses a while ago.
This issue may already be "logged".

BTW, is there a list of errata that we can see? I expect we may
get multiple reports of the same issues and it will be good if
there is a way to make the list of issues and responses/interpretations
visible.

John H.

> <html>
> As you have pointed out, the examples do match the LRM. The syntax in =
> the
> examples need to be corrected and filed as errata. 
> Surrendra 
> At 09:10 PM 5/2/2004 -0400, you wrote: 
> <blockquote type=3Dcite class=3Dcite cite> size=3D2>LRM
> requires parentheses when sequence match item is used.  Yet,
> 
> LRM document is not consistent with this requirement.  
> 17.8 Manipulating data in a sequence 
> ... 
> sequence_expr ::=3D 
> ... 
> | (
> expression_or_dist {,
> sequence_match_item }
> color=3D"#FF0000">)
> [ boolean_abbrev ] 
> | (
> sequence_expr {,
> sequence_match_item}
> color=3D"#FF0000">)
> [ sequence_abbrev ] 
> ... 
>   
> a ##1
> color=3D"#FF0000">( size=3D2>b[->1],
> x =3D
> e color=3D"#FF0000">)
> ##1 c[*2] 
> sequence data_check; 
>   int x; 
>   a ##1 color=3D"#FF0000">!a, x =3D
> data_in ##1 !b[*0:$] ##1 b
> && (data_out =3D=3D x); 
> endsequence 
>   
> Shouldn't =
> that
> line be with parentheses, such as:
> 
>  a ##1 color=3D"#FF0000">(!a, x =3D
> data_in) ##1 !b[*0:$] ##1 b
> && (data_out =3D=3D x); 
> property data_check_p 
>   int x; 
>   a ##1 color=3D"#FF0000">!a, x =3D
> data_in |=3D> !b[*0:$] ##1 =
> b
> && (data_out =3D=3D x); 
> endproperty 
> Shouldn't =
> that
> line be with parentheses, such
> as: 
>   a ##1 color=3D"#FF0000">(!a, x =3D
> data_in) |=3D> !b[*0:$] ##1 =
> b
> && (data_out =3D=3D x); 
> ... 
> sequence rep_v; 
>   int x; 
>   =E2=80=98true,x =3D 0 ##0 
>   (!a [* 0:$] ##1
> a, x =3D
> x+data)[*4] ##1 b ##1 c =
> &&
> (data_out =3D=3D x); 
> endsequence 
> Shouldn't =
> that
> line be with parentheses, such
> as: 
>  (!a [* 0:$] ##1
> (a, x =3D
> x+data))[*4] ##1 b ##1 c =
> &&
> (data_out =3D=3D x); 
> size=3D1>---------------------------------------------------------------=
> -------------- 
> Ben Cohen Trainer, Consultant, Publisher (310) 721-4830 
> <a href=3D"http://www.vhdlcohen.com/">http://www.</a>vhdlcohen<a =
> href=3D"http://www.vhdlcohen.com/">.com/</a>
> vhdlcohen@aol.com 
> Author of following textbooks: 
> * Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, =
> 2004 isbn 0-9705394-6-0 
> * Real Chip Design and Verification Using Verilog and VHDL, 2002 =
> isbn 0-9705394-2-8 
> * Component Design by Example ", 2001 isbn =
> 0-9705394-0-1 
> * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn =
> 0-7923-8474-1 
> * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn =
> 0-7923-8115 
> ------------------------------------------------------------------------=
> ------</blockquote>
> <x-sigsep></x-sigsep>
> 
> ********************************************** 
> Surrendra A. Dudani 
> Synopsys, Inc. 
> 377 Simarano Drive, Suite 300 
> Marlboro, MA 01752 
> Tel:   508-263-8072 
> Fax:   508-263-8123 
> email: Surrendra.Dudani@synopsys.com  
> **********************************************</html>
Received on Mon May 3 08:49:14 2004

This archive was generated by hypermail 2.1.8 : Mon May 03 2004 - 08:49:24 PDT

Re: [sv-ac] SVA: LRM 17.8 // Parentheses with sequence_match_item