[sv-ac] Comments to SystemVerilog_3.1a_draft6_clean Section 17 Assertions.doc

From: <Wolfgang.Ecker@Infineon.Com>
Date: Thu Apr 22 2004 - 09:11:51 PDT

Hi SystemVerilog Folks,

please find attached a summary of comments and improvement proposals to
the SystemVerilog
LRM. Mostly, they result from my study of the assertion chapter
(gratulations to the author's)), some
items (as inconsisten X,Z mapping) cover also other chapters.

Unfortunately, I cannot attend the phone conference on Monday, because I
am in the plane to San Franzisco.
If you plan a meeting in the evening, please let me know. I offer to
discuss the items face to face.

Kind regards,
Wolfgang Ecker

 <<Comments to SystemVerilog_3.1a_draft6_clean Section 17
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Received on Thu Apr 22 09:12:14 2004

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