RE: [sv-ac] meeting on 3/8

The excerpted BNF was from an earlier draft of Annex A (that was
not correctly removed from Syntax 10-1 in draft 5). For the current
version see A.2.7 in draft 5 or in --

    http://www.eda-twiki.org/sv/Changes_draft5/LRM_Changes_A_BNF.html

-- Brad

-----Original Message-----
From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org]On Behalf Of
Miller Hillel-R53776
Sent: Monday, March 08, 2004 8:35 AM
To: Miller Hillel-R53776; 'Surrendra Dudani'; sv-ac@eda.org
Subject: RE: [sv-ac] meeting on 3/8

Hi,

My proposal for the first item is to use the current bnf for SystemVerilog
task/function formal parameter description:

tf_port_list ::=
tf_port_item { , tf_port_item }
tf_port_item ::=
{ attribute_instance } tf_input_declaration
| { attribute_instance } tf_output_declaration
| { attribute_instance } tf_inout_declaration
| { attribute_instance } tf_ref_declaration
| { attribute_instance } [ signing ] { packed_dimension }
list_of_tf_variable_identifiers
| { attribute_instance } data_type list_of_tf_variable_identifiers
tf_port_item ::=
{ attribute_instance }
[ tf_port_direction ] data_type_or_implicit
port_identifier variable_dimension [ = expression ]

I drop the second issue, my mistake.

Hillel

-----Original Message-----
From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org]On Behalf Of Miller
Hillel-R53776
Sent: Monday, March 08, 2004 9:00 AM
To: 'Surrendra Dudani'; sv-ac@eda.org
Subject: RE: [sv-ac] meeting on 3/8

Hi,

I would like to discuss the following items:

1) No datatypes of formal paramaters in property definitions. Can we add
these datatypes?
2) Confusing syntax, according to the BNF you can only do one local variable
assignment at a time and in the examples you could do more:

sequence_match_item ::=
variable_assignment <------------- does this mean one
assignment? where does the comma come in?
| subroutine_call

there is a an example:

sequence s8;
int x,y;
(a ##1 b, x = data, y = data1 ##1 c)
and (d ##1 'true, x = data ##0 (e==x))) ##1 (y==data2);
// legal since y is in the difference
endsequence

3)

-----Original Message-----
From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org]On Behalf Of Surrendra
Dudani
Sent: Friday, March 05, 2004 6:47 PM
To: sv-ac@eda.org
Subject: [sv-ac] meeting on 3/8

I would like to discuss the following items in Monday's meeting:
1) Currently, expression (instead of expression_or_dist) is used in two
constructs: if-else and disable iff. We can possibly change them to
expression_or_dist.
2) Replacing variable_assignment in inc_or_dec_expression as

sequence_match_item ::=
operator_assignment
| inc_or_dec_expression
| subroutine_call

This change will allow other kinds of assignment short cuts already allowed
in SV.
3) Moving the implication section (17.7.11) under the property section
(17.11), as suggested by Adam.
4) list of errata that I have compiled so far.

Surrendra

**********************************************
Surrendra A. Dudani
Synopsys, Inc.
377 Simarano Drive, Suite 300
Marlboro, MA 01752

Tel: 508-263-8072
Fax: 508-263-8123
email: Surrendra.Dudani@synopsys.com
**********************************************
Received on Tue Mar 9 09:23:21 2004