Subject: [sv-ac] Text eratta for SV-AC LRM.
From: Adam Krolnik (krolnik@lsil.com)
Date: Fri Dec 12 2003 - 10:38:13 PST
Hello All;
This should be considered in the final LRM review...
Adam
-------- Original Message --------
Subject: [sv-ac] Erratta in section 17.6, 17.10
Date: Thu, 06 Nov 2003 09:34:06 -0600
From: Adam Krolnik <krolnik@lsil.com>
To: sv-ac@eda.org
Good morning;
1. Omission of formal_list_item in BNF syntax boxes.
Reading the 3.1_final spec, the BNF for sequence definition and property definition
omits the production formal_list_item.
This production shows the format of formal arguments to sequences and properties
and shows how default values can be specified. Default values are not described
or shown in any examples. Thus we need to include the BNF at the least, and add
some text to explain or demonstrate this.
My previous mail added a little about default argument values, we may want an example
or two.
2. Section 17.5 (Sequences) title is misleading.
This section would be better named "Sequence expressions", mirroring section 17.4
(Boolean expressions). Sequence (definition) is discussed in section 17.6 and is
followed by sequence operatoions. Thus the subsection titles would be
17.4 Boolean expressions
17.5 Sequence expressions
17.6 Declaring sequences
17.7 Sequence operations
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
Co-author "Assertion Based Design"
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