Subject: RE: [sv-ac] Initial proposal text for messages in sequences.
From: David W. Smith (David.Smith@synopsys.com)
Date: Wed Dec 10 2003 - 11:01:15 PST
Hi John and Adam,
Just as a process clarification. All technical changes for 3.1a were
supposed to be complete on Dec. 1. This was extended to next week so that
each could complete their work. At that time all technical changes to the
LRM are supposed to be complete and the final draft of technical changes
will be done from whatever is complete by the last SV-AC meeting of that
week. I believe that SV-BC and SV-EC will be wrapped up by Monday the 15th.
Draft 2 is in process and draft 3, the final technical draft, will be based
on the conclusion of all committee work next week.
There will be no more technical changes accepted after next week. The next
stage of the process is to complete editorial review (grammar, consistency,
clarity) review and approve the LRM to be sent to the board by 24 January.
This is the schedule that each committee has approved in their operating
guidelines.
The actual closing of new submissions was 15 September. The only items we
should be working on now is finalizing the extensions and wrapping up
errata.
I thought this would be a useful review since it was not clear in the email
exchange that the current deadlines for each committee were clearly
understood. I hope this helps.
Regards
David S.
-----Original Message-----
From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of John
Havlicek
Sent: Wednesday, December 10, 2003 10:10 AM
To: krolnik@lsil.com
Cc: john.havlicek@motorola.com; sv-ac@eda.org
Subject: Re: [sv-ac] Initial proposal text for messages in sequences.
Adam and All:
I think it is achievable to put my suggestion into 3.1a.
Do you have issues with it or is it unclear whether my
suggestion is a good step to take right now?
Briefly, my suggestion was to allow attaching the messages to
booleans and sequences with the comma syntax and with the semantics
that says the message executes only if the boolean or sequence
matches (i.e., the "passing" mode).
This way there will be some debugging capability in the 3.1a
language.
In the next revision, we would work on getting the failing mode
defined and the syntax to represent it, as well as the single
error messages for properties.
Best regards,
John H.
> Date: Wed, 10 Dec 2003 10:46:22 -0600
> From: Adam Krolnik<krolnik@lsil.com>
> X-Accept-Language: en-us, en
> Cc: <sv-ac@eda.org>
> Sender: owner-sv-ac@eda.org
> Precedence: bulk
>
>
>
> Hi John;
>
> Thank you for the excellent critique of this attempt at providing the
ability
> to provide context of the failure back to the user.
>
> I suggest that this be one of the first issues that the committe works on
for
> the next SV revision.
>
> Adam Krolnik
> Verification Mgr.
> LSI Logic Corp.
> Plano TX. 75074
> Co-author "Assertion Based Design"
>
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