[sv-ac] sampled value function and dynamic auomatic references

LRM has removed restrcition that automatic vars cannot be used in 
sampled value function. (http://www.verilog.org/mantis/view.php?id=4252)
Proposed solution has sens for $past but what aoub other sampled value 
function how those should work with auomatic variables? ie
function automatic foo;
     int a;
     bit clk;
     $display($rose(a, (posedge clk);
endfunction

LRM also do not mention about dynamic var ie:
class C;
   int a;
   bit clk;
   function automatic foo;
     $display($past(a, (posedge clk);
   endfunction
endclass

C c;
     iniitial $display($past(c.a, (posedge c.clk);

How should code like above behave?

DANiel

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