RE: [sv-ac] checker: why are parameters not allowed? Need to file a mantis?

From: Korchemny, Dmitry <dmitry.korchemny@intel.com>
Date: Wed May 23 2012 - 05:04:51 PDT

Hi Ben,

This mantis already exists, see http://www.eda-twiki.org/svdb/view.php?id=2111.

However, IMO there is little added value in introducing parameters to checkers. Checker invocation should be similar to a property's syntax, and not to a module's.

Say, you want to check that a request will be granted in n cycles. Then it is very natural to write it like this:

// invocation
request_granted rg1(req, gnt, 4, clk);

checker request_granted(request, grant, n, event clk);
                a: assert property (@clk request |-> ##n grant);
endchecker

Rather than to use this ugly syntax:
request_granted #(4) rg1 (req, gnt, clk);

checker request_granted #(n) (request, grant, event clk);
                a: assert property (@clk request |-> ##n grant);
endchecker

What is a benefit of introducing parameters for checkers in your opinion? Do you have a specific example?

Thanks,
Dmitry

From: Ben Cohen [mailto:hdlcohen@gmail.com]
Sent: Tuesday, May 22, 2012 22:12
To: sv-ac@eda-stds.org; Korchemny, Dmitry; Eduard Cerny
Subject: [sv-ac] checker: why are parameters not allowed? Need tofile a mantis?

Dmitry,
Why are parameters not allowed in checkers, in the same style as module?
If we do allow them, would that bring more consistency in design style, and possibly simplify the design of tools because of this parallelism to modules?
Before I file a mantis for future exploration of this, I would like to hear your comments.
Thanks,
Ben
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Received on Wed May 23 05:06:34 2012

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