[sv-ac] SVA 16.17: Is the expect statement legal in a class using virtual interface?

Question relates to file uploaded at
http://www.eda-stds.org/svdb/view.php?id=4119

LRM states that "The expect statement can appear anywhere a wait statement
(see 9.4.3) can appear".
A wait statement can appear in a class within a task. Frameworks, like
UVM, use virtual interfaces.
Thus, I would think that the following code is legal, from an LRM
viewpoint. Below is a copy of the class
with the expect statement. If a simulator does not compile/elaborate on
this code, would that be a not supported feature or simply because it is a
violation of the LRM? I think that this code should be legal. I need
your feedback as to why it is (or it is not) legal.

class c_driver;
    virtual interface master_if.drvr_if_mp v_if;
    function new(); endfunction : new

    task continue2(); //..
        $display("%t, continue2", $time);
    endtask : continue2 // What to do if response to abt is the abtED
    task abt_error();
        $display("%t, abt_error", $time); //…
    endtask : abt_error // What to do if response to abt is not abtED

    task drive();
        // code..
        v_if.data_in <= 4'b1010;
        v_if.ld <= 1'b1;
        @(v_if.driver_cb)
         v_if.ld <= 1'b0;
        exp0: expect ( @(v_if.driver_cb)
                      v_if.mst_abt ##[2:8] v_if.slv_resp)
        continue2(); // pass action block
        else abt_error(); // fail action block
    endtask : drive

endclass : c_driver
Ben

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