[sv-ac] RE: Feeding checker result into module

Hi Dana,

Why do we need to add if (scan)?

Thanks,
Dmitry

From: Dana Fisman Ofek [mailto:Dana.Fisman@synopsys.com]
Sent: Wednesday, January 18, 2012 17:35
To: Korchemny, Dmitry
Cc: sv-ac@eda-stds.org
Subject: RE: Feeding checker result into module

Hi Dmitry,

I am not sure it is that much of an overkill. I would like to see some use of scan later in the module, after checker is instantiated. Perhaps instead of introducing res and having always @(posedge clk) scan <= res we can add something like if (scan)... to your rewrite.

Dana

From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of Korchemny, Dmitry
Sent: Wednesday, January 18, 2012 8:30 AM
To: sv-ac@eda-stds.org
Subject: [sv-ac] Feeding checker result into module

Hi all,

We have the following example in 17.3:

checker mutex (logic sig, event clock, output bit failure);
assert property (@clock $onehot0(sig)) failure = 1'b0; else failure = 1'b1;
endchecker : mutex
module m(wire bus, logic clk);
logic res, scan;
// ...
mutex check_bus(bus, posedge clk, res);
always @(posedge clk) scan <= res;
endmodule : m

It looks to me that this example is an overkill, and should be rewritten as:
checker mutex (logic sig, event clock, output bit failure);
assert property (@clock $onehot0(sig)) failure = 1'b0; else failure = 1'b1;
endchecker : mutex
module m(wire bus, logic clk);
logic scan;
// ...
mutex check_bus(bus, posedge clk, scan);
endmodule : m

What do you think?

Thanks,
Dmitry
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