I have uploaded a new version addressing the issues below, at http://www.verilog.org/mantis/view.php?id=3206 . The .doc version has change tracking turned on, so you can quickly see the differences.
These changes are all pretty simple, so I'm hoping we can voice-vote them tomorrow. Please try to take a look before the meeting.
-----Original Message-----
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The proposal was opposed by the Champions in the email vote which ended
October 31, 2011.
Shalom
The proposal defines vpiIsFinal in the VPI diagram, but does not define it
in
Annex M.
Friendly amendments:
In example in 16.4.2, "input bit" is not legal (in 2 places). Make them
"input
logic". (Keywords should be bold.)
"always_comb" should also be bold in the text, twice.
Immediate assertions VPI diagram is in 37.53 in Draft 2, not 37.51.
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