RE: [sv-ac] Call to vote: Due September 12 (resend with correct version of the proposal)

Hi Tom,

Please, see my comments below.

Thanks,
Dmitry

-----Original Message-----
From: Thomas J Thatcher [mailto:thomas.thatcher@oracle.com]
Sent: Monday, September 12, 2011 20:25
To: Korchemny, Dmitry
Cc: 'sv-ac@eda-stds.org'
Subject: Re: [sv-ac] Call to vote: Due September 12 (resend with correct version of the proposal)

My Vote.

Tom

> Mantis 2093 __x__ Yes ____ No
>
> http://www.eda-stds.org/mantis/view.php?id=2093
> <http://www.eda-stds.org/mantis/view.php?id=2093%20>
>
> http://www.eda-stds.org/mantis/file_download.php?file_id=5406&type=bug
> <http://www.eda-stds.org/mantis/file_download.php?file_id=5406&type=bu
> g>

The first motivational example shows a checker output, but it doesn't show how that output is being used to do something useful.
[Korchemny, Dmitry] Modified the example.

In the second motivational example, the checker model_fsm does not use the variable state anywhere inside. I suggest omitting that port from the checker port list. In both the before and after examples, there are no input ports for signals or events that might cause a state change.
[Korchemny, Dmitry] state is used in the checker. Note the assertion:
a1: assert property (astate == IDLE <-> *state* in {IDLE1, IDLE2});

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