RE: [sv-ac] comments on Surrendra's corrections

Subject: RE: [sv-ac] comments on Surrendra's corrections
From: Surrendra Dudani (Surrendra.Dudani@synopsys.com)
Date: Fri Nov 07 2003 - 12:44:19 PST

Hi Bassam,John
Regarding Fig. 17-12, the values shown are sampled values of the signals. The LRM explains what sampled values are in Fig. 17-1. In Fig. 17-3, simulation values are explicitly shown for value change expressions. Once explained, the LRM doesn't show the raw simulation values of signals. All values are sampled with respect to the clock and shown.This is also mentioned  again

Each time a data phase is true, a match for data_phase is recognized. The attempt at clock tick 6 is illustrated
in Figure 17-13. The values shown for the signals are the sampled values with respect to the clock. At clock
tick 6, data_end is true because stop gets asserted while irdy is asserted.

I think when a figure appears like a waveform, perhaps, people associate it with simulation values, not sampled values.
There used to be a big note about this, but somehow it disappeared (don't know why).
Should we add back a note explaining that after Figure 17-1, all values are sampled values?

Surrendra
At 12:08 PM 11/4/2003 -0800, you wrote:
Hi John,

Thanks for catching this! Yes you are right I think the burst_mode edge
*needs some pushing to the left, that would be the minimal change to
this figure*,(the default here is the #1step sampling so this needs a
push). I think we caught this in Figure 17-1 a while back with the
"req", let's update all of 'em, we missed these.

** I agree with all of John's corrections (1.17, <statements>; already
has a semicolon).

Good catch John, this would've been one huge headache!

-Bassam.

--
Dr. Bassam Tabbara
Technical Manager, R&D
Novas Software, Inc.

http://www.novas.com
(408) 467-7893

> -----Original Message-----
> From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On
> Behalf Of John Havlicek
> Sent: Sunday, November 02, 2003 9:35 AM
> To: sv-ac@eda.org
> Subject: [sv-ac] comments on Surrendra's corrections
>
>
> All:
>
> Below are my comments on Surrendra's suggested changes in
> SV_AC_LRM_corrections_10.12.pdf.
>
> Best regards,
>
> John H.
>
> ==============================================================
> ==========
>
> 1.1  I agree.
>
> 1.2  I agree.
>
> 1.3  I agree.
>
> 1.4  I agree.
>
> 1.5  I agree.
>
> 1.6  I agree.
>
> 1.7  I agree.
>
> 1.8  I agree.
>
> 1.9  I agree.
>
> 1.10 I agree, but I'm not happy about the way the picture
>      fig 17-12 seems to confuse the sampling of values. 
>      Sampling at mclk, it looks to me as though $fell burst_mode
>      should be true at time 3, not time 2.  Etc., etc., etc.
>
>      I think the same goes for fig 17-11. 
>
>      What do other people think?
>
> 1.11 I agree.  With this change, the definition of property r2 is
>      the same as that of property r3.  However, I think that
>     
>         property r3;
>            @(posedge mclk)(q != d);
>         endproperty
>         always @(posedge mclk) begin
>            if (a) begin
>               q <= d1;
>               r3_p: assert property (r2);
>            end
>         end
>
>      should be
>
>         property r3;
>            @(posedge mclk)(q != d);
>         endproperty
>         always @(posedge mclk) begin
>            if (a) begin
>               q <= d1;
>               r3_p: assert property (r3);
>            end
>         end
>
> 1.12 I agree.
>
> 1.13 I agree.
>
> 1.14 I agree.
>
> 1.15 I agree, but change "atleat" to "at least".  I have already said
>      that I think these figures are misleading representations of the
>      signal sampling.
>
> 1.16 I agree, same caveat about the sampling in the diagrams.
>
> 1.17 I agree.  Probably there should not be a semicolon after
> <statements>.
>
> 1.18 I agree.
>
> 1.19 I agree.
>
> 1.20 I agree.
>



**********************************************
Surrendra A. Dudani
Synopsys, Inc.
377 Simarano Drive, Suite 300
Marlboro, MA 01752

Tel:   508-263-8072
Fax:   508-263-8123
email: Surrendra.Dudani@synopsys.com 
**********************************************

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