[sv-ac] 3766: 17.6 : Error in use of variable in example

New Mantis http://www.eda-stds.org/svdb/view.php?id=3766

Summary0003766: 17.6 : Error in use of variable in example DescriptionError
in use of variable in example in section 17.6 Covergroups in checkers.
checker op_test (logic clk, vld_1, vld_2, logic [3:0] opcode);
...
@(posedge clk) vld_1 ##1 (vld2, cg_op_1.sample(opcode_d1));
SHOULD USE "vld_2" instead of "vld2"

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