Subject: RE: [sv-ac] unnecessary semicolon?
From: Surrendra Dudani (Surrendra.Dudani@synopsys.com)
Date: Wed Nov 05 2003 - 11:46:32 PST
There were two reasons to require this semicolon:
1) to be compatible with Verilog as all statements and definitions require
terminators
2) to allow for future additions to the definition
Surrendra
At 12:19 PM 11/4/2003 -0800, you wrote:
>John/Adam,
>
>Which semicolon you mean ? Anyway, both as I recall were additions by
>the "syntax committee" under "like-Verilog" additions. So I think (vote
>?) better stick to as is.
>
>sequence e1; // <<<<<< this one ?
>@(posedge clk) $rose(ready) ##1 proc1 ##1 proc2 ; // <<< I think you
>mean this one, right ?
>endsequence
>
>Thx.
>-Bassam.
>
>--
>Dr. Bassam Tabbara
>Technical Manager, R&D
>Novas Software, Inc.
>
>http://www.novas.com
>(408) 467-7893
>
> > -----Original Message-----
> > From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On
> > Behalf Of Adam Krolnik
> > Sent: Monday, November 03, 2003 1:57 PM
> > To: john.havlicek@motorola.com
> > Cc: sv-ac@eda.org
> > Subject: Re: [sv-ac] unnecessary semicolon?
> >
> >
> >
> >
> > I'll vote for optional semicolons.
> >
> > Precedence for the next standard...
> >
> > Adam
> >
> >
> >
**********************************************
Surrendra A. Dudani
Synopsys, Inc.
377 Simarano Drive, Suite 300
Marlboro, MA 01752
Tel: 508-263-8072
Fax: 508-263-8123
email: Surrendra.Dudani@synopsys.com
**********************************************
This archive was generated by hypermail 2b28 : Wed Nov 05 2003 - 11:47:08 PST