Subject: Re: [sv-ac] unnecessary semicolon?
From: John Havlicek (john.havlicek@motorola.com)
Date: Tue Nov 04 2003 - 14:03:48 PST
Hi Bassam:
You are right, it is the second semicolon, the one that comes
just before the "endsequence" keyword, that I mean.
Of course, this is not a big deal; no one is going to enter SVA in
any beauty contests. :)
John H.
> Reply-To: <bassam@novas.com>
> From: "Bassam Tabbara"<bassam@novas.com>
> Cc: <sv-ac@eda.org>
> Date: Tue, 4 Nov 2003 12:19:11 -0800
> Organization: Novas Software, Inc.
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>
> John/Adam,
>
> Which semicolon you mean ? Anyway, both as I recall were additions by
> the "syntax committee" under "like-Verilog" additions. So I think (vote
> ?) better stick to as is.
>
> sequence e1; // <<<<<< this one ?
> @(posedge clk) $rose(ready) ##1 proc1 ##1 proc2 ; // <<< I think you
> mean this one, right ?
> endsequence
>
> Thx.
> -Bassam.
>
> --
> Dr. Bassam Tabbara
> Technical Manager, R&D
> Novas Software, Inc.
>
> http://www.novas.com
> (408) 467-7893
>
> > -----Original Message-----
> > From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On
> > Behalf Of Adam Krolnik
> > Sent: Monday, November 03, 2003 1:57 PM
> > To: john.havlicek@motorola.com
> > Cc: sv-ac@eda.org
> > Subject: Re: [sv-ac] unnecessary semicolon?
> >
> >
> >
> >
> > I'll vote for optional semicolons.
> >
> > Precedence for the next standard...
> >
> > Adam
> >
> >
> >
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