RE: [sv-ac] Bug in 16.13.6 example

Hi Stu,

This is indeed a bug. We will add a bug note.

Thanks,
Dmitry

From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of Stuart Sutherland
Sent: Monday, August 08, 2011 19:39
To: sv-ac@eda-stds.org
Subject: [sv-ac] Bug in 16.13.6 example

I just noticed that there is a mistake in the example in clause 16.13.6, just before figure 16-14. The example shows a cycle delay range of ##[1,5]. It should be ##[1:5] (a colon instead of a comma). This part of the example was modified in Mantis 2722, which was entered in Draft 1. Another bug in the example was fixed in Draft 2. Mantis 2722 is still open for final review, so I suggest a bug note be added to correct the editing and mantis 2722 be sent back to the editor.

Stu
~~~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland
Sutherland HDL, Inc.
stuart@sutherland-hdl.com
503-692-0898
www.sutherland-hdl.com<http://www.sutherland-hdl.com>

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