[sv-ac] Rev 0 proposal for 3206 (deferred assertions are sensitive to glitches) posted

Hi guys-

I have posted the proposal at http://www.verilog.org/mantis/view.php?id=3206 . This is an attempt to implement the idea we discussed in email, where a new class of deferred assertions called "final assertions" is available. These assertions mature in the Postponed region, and thus are guaranteed to not iterate with the testbench.

Please take a look & send comments/suggestions if interested. We can discuss at Tuesday's SV-AC.

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