Subject: Fwd: [sv-ac] Erratta on implication operator.
From: Arif Samad (Arif.Samad@synopsys.com)
Date: Fri Oct 31 2003 - 15:09:01 PST
Adam had sent this erratum some time ago.
This was left off the original errata list.
Please review this and send any comments.
We can go over this and take a vote at
one of the upcoming meetings.
Regards,
Arif
--------------
>Date: Tue, 26 Aug 2003 09:02:57 -0500
>From: Adam Krolnik <krolnik@lsil.com>
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>To: sv-ac@eda.org
>Subject: [sv-ac] Erratta on implication operator.
>Sender: owner-sv-ac@eda.org
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>
>
>
>Good morning;
>
>I have an erratta concerning the implication operator.
>
>To this list of points in 17.7.11, I would like to add the following
>before the last
>point (which may be removed pending other proposals.)
>
>
>WAS:
><nothing>
>
>Proposed:
>
>o Only zero or one match of the consequent sequence_expr will occur. There
>is an implicit first_match operator applied to the consequent. For example.
>
> antecedent_expr |-> consequent_expr
>
>is really evaluated as:
>
> antecedent_expr |-> first_match (consequent_expr)
>
>
>There is a reference to this in section 17.10 (pg 176.) but it should be
>explicitly
>noted here next to the operator, in addition to the section on properties.
>
> Thanks.
>
> Adam Krolnik
> Verification Mgr.
> LSI Logic Corp.
> Plano TX. 75074
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