RE: [sv-ac] Glitch-free deferred assertions

Hi Karen,

We will discuss this in our meeting. What about #1step?

Thanks,
Dmitry

From: Karen Pieper [mailto:karen_l_pieper@yahoo.com]
Sent: Monday, July 04, 2011 16:09
To: Korchemny, Dmitry
Cc: sv-ac@eda-stds.org; Rich, Dave; Gordon Vreugdenhil (gordonv@model.com)
Subject: Re: [sv-ac] Glitch-free deferred assertions

I'd suggest #end or #stable something similar because #1 has other meaning elsewhere in the language.

Just a thought.

Karen

Sent from my iPhone

On Jul 4, 2011, at 5:41 AM, "Korchemny, Dmitry" <dmitry.korchemny@intel.com<mailto:dmitry.korchemny@intel.com>> wrote:
Hi all,

In our F2F we discussed glitch-free deferred assertions, and the suggestion was to mature these assertions in the Postponed region. This will, however, introduce a backward incompatibility, and there may be people who are using the action blocks of deferred assertions to trigger events in the test bench.

Would the introduction of a new flavor of the deferred assertion work? I am talking about leaving the existing deferred assertions as they are, e.g.,

assert #0 (a) …;

and to introduce a new flavor with the following syntax:

assert #1 (a) …;

This new kind of deferred assertions works exactly as the existing one, except for the fact that they mature in the Postponed region and that their action blocks cannot change any values (i.e., they are essentially limited to issuing messages).

This will introduce rather a small addition to the LRM, and will not break the backward compatibility. This is somewhat similar to the strobe option in covergroups. What do you think?

Thanks,
Dmitry
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