[sv-ac] 3195 and 3476 need to be addressed in our discussions

Dmitry,
I feel that we need to add the following mantises into our discussions
*3195: Local variables flow out issue in and/or/intersect/implies*
 3195 offers the capability to account for the flow through of local
variables from an antecedent into consequent when
 specifying an assertion using timing points specified by sequences or
delays.

*3476: Make drivers of inout ports accessible*
 3476 addresses a deficiency in SVA in that 1800'2009 does not address the
proper handling of bidirectional ports of modules.
I understand that we we need approval to work on this, as it involves
another committee to look into the introduction of new system level
functions. Thus, I am asking you to pursue this avenue for us to have this
capability. I would like to close this gap in dealing with assertions with
bidirectional ports.

Thanks,
Ben Cohen SystemVerilog.us

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