Subject: RE: [sv-ac] Property definition in $root
From: Bassam Tabbara (bassam@novas.com)
Date: Tue Oct 28 2003 - 15:39:11 PST
I don't think there is any concern here. You can do the same thing with
packages (aka "library scheme"). I think the cleanup of $root should be
encouraged to make separate compilation possible.
-Bassam.
-- Dr. Bassam Tabbara Technical Manager, R&D Novas Software, Inc.http://www.novas.com <http://www.novas.com/> (408) 467-7893
-----Original Message----- From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of Armoni, Roy Sent: Tuesday, October 28, 2003 8:43 AM To: System Verilog Assertion Subject: [sv-ac] Property definition in $root
Hi everyone,
I see in <http://www.eda-twiki.org/sv-bc/sep_comp/Packages_Sep_V5.pdf> http://www.eda-twiki.org/sv-bc/sep_comp/Packages_Sep_V5.pdf that BC are proposing to disallow assert statements in $root. I believe this is o.k. as long as it is allowed to define properties in $root, otherwise, we may need to compile the same property over and over in every module.
What do you think?
Regards,
Roy
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