[sv-ac] sv-ac: quick clarification questions of checker update regions

Questions: or model shown below:
1) When is "x" sampled? Active Region
2) In what region is "z" changed? In the Reactive?
3) are my comments correct?

checker check(bit a, b, event clk, ...);
  bit x, y, z, v;
  assign x = a & b; // legal, changed in the Reactive Region?
  always_comb
    y = a & b; // legal, changed in the Reactive Region?
  always_ff @clk
    z <= !x; // , x sampled in active region? z changed in Reactive?
endchecker : check

module m;
   logic clk=0, a, b;
   initial forever #10 clk=!clk;
   check chk1(a, b, posedge clk);
    ...
endmodule : m
Ben

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