Hi Ben:
I took a brief look at 3195 and have some high-level concerns.
I find the choice to use the keyword automatic for these variables confusing. Automatic has meaning in the rest of the LRM and it doesn't mean a variable that can only be assigned once. I understand the desire to not add keywords, but I don't think the choice of automatic works well.
The restrictions for the use seem quite severe (only w/ implies). It is clear that you have a specific use case and coding style in mind. The proposal allows for this use case/coding style and nothing more. Have you considered other operators where this might be useful (|-> for instance)? If the capability is useful, then I would prefer to see a proposal that enables the functionality across all SVAs as appropriate.
I would expect to see some changes to the formal semantics for this, but those are missing from the proposal.
Thanks,
Scott
From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of ben cohen
Sent: Thursday, May 12, 2011 12:59 AM
To: Korchemny, Dmitry
Cc: sv-ac@eda-stds.org
Subject: Re: [sv-ac] Items would like to address at upcoming meetings
Dmitry,
Thanks. Can we add 3552 and 3195 to next week's agenda?
On 3478, can you please seek permission, as this issue deals with a very important missing feature of SVA to address bi-directional IOs.
Thanks,
Ben
On Wed, May 11, 2011 at 10:53 PM, Korchemny, Dmitry <dmitry.korchemny@intel.com<mailto:dmitry.korchemny@intel.com>> wrote:
Hi Ben,
You are welcome to address issues 3552 and 3195. We are not authorized to address 3478.
Thanks,
Dmitry
From: ben cohen [mailto:hdlcohen@gmail.com<mailto:hdlcohen@gmail.com>]
Sent: Thursday, May 12, 2011 02:31
To: sv-ac@eda-stds.org<mailto:sv-ac@eda-stds.org>; Korchemny, Dmitry
Subject: [sv-ac] Items would like to address at upcoming meetings
Dmitry,
Below is a list of items I would like us to address:
Make drivers of inout ports accessible
http://www.eda-stds.org/svdb/view.php?id=3478
Uploaded a new version of the mantis.
I also uploaded a diagram (extdriver.pdf) clarifying the meaning of those functions in a DUT instantiated in a testbench.
16.14.6 Sequence methods // .triggered need further clarification
http://www.eda-stds.org/svdb/view.php?id=3552
Made some updates
Local Variables Flow Out Issue in and/or/intersect/implies
http://www.eda-stds.org/svdb/view.php?id=3195
Made some updates
I also welcome comments on these topics.
Ben Cohen SystemVerilog.sv
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