[sv-ac] RE: Call to vote: Due May 2

Hello Dmitry,

please see my vote below:

ed

Mantis 3213 __X__ Yes ____ No

http://www.verilog.org/mantis/view.php?id=3213

http://www.eda-stds.org/mantis/file_download.php?file_id=4961&type=bug

Small issues:
last line on pp 3: ... of a concurrent ?? context is stricken out...
above 16.6 on pp5: missing "." at the end of sentence ... from procedural code (see 16.15.6)

Other:
"Use of $sampled in a disable iff clause is meaningful since the disable condition is not evaluated in the concurrent context (see 16.13)."
I that is the case, If I wish to use a sampled value in disable iff, how can it be done if it is meaningless? That should return the proponed/postponed value. Perhaps this is what is meant, but then it is not meaningless.

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