[sv-ac] RE: Call to vote: Due March 28 (reminder)

No, it's supposed to be an 'and'.

--------------------------------
Jacob M. Katz | jacob.katz@intel.com<mailto:jacob.katz@intel.com> | Work: +972-4-865-5726 | iNet: (8)-465-5726

From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of Prabhakar, Anupam
Sent: Monday, March 28, 2011 22:53
To: sv-ac@eda-stds.org
Subject: [sv-ac] RE: Call to vote: Due March 28 (reminder)

Mantis 2476 __X__ Yes ____ No
http://www.verilog.org/mantis/view.php?id=2476
http://www.eda-stds.org/mantis/file_download.php?file_id=4856&type=bug

Mantis 3191 __X__ Yes ____ No

http://www.eda-stds.org/mantis/view.php?id=3191
http://www.eda-stds.org/mantis/file_download.php?file_id=4855&type=bug

Friendly amendment
The change in 16.8 (top of page 2)
- The reference to the formal argument stands as the sequence_instance in a sequence_method_call. The reference to the formal argument stands as the operand sequence in a sequence_method_call, and the actual argument is a named sequence instance.

I think there should be an 'or' instead of an 'and'.
The reference to the formal argument stands as the operand sequence in a sequence_method_call or the actual argument is a named sequence instance.

Anupam

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