Re: [sv-ac] modport usage in assertions

Shalom,
Will this be resolved by the time the new version of p1800 comes out?
Ben

On Tue, Mar 22, 2011 at 10:54 AM, Bresticker, Shalom <
shalom.bresticker@intel.com> wrote:

> Ben,
>
>
>
> This has come up to SV-BC a couple of times recently, and we agree it is
> not legal today.
>
> A vendor that allows it is being lenient, but no one can complain about a
> tool that rejects it.
>
> Some people think it should be legal, but as I wrote, we agree that today
> it is not.
>
>
>
> Regards,
>
> Shalom
>
>
>
> *From:* owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] *On Behalf Of *ben
> cohen
> *Sent:* Tuesday, March 22, 2011 7:29 PM
> *To:* sv-ac@eda.org; Korchemny, Dmitry
> *Subject:* [sv-ac] modport usage in assertions
>
>
>
> Given the following:
>
> *interface* fifo_if(input wire clk,
>
> input wire reset_n);
>
> ....
>
> wire [WIDTH-1:0] data_in;
>
> modport fslave_if_mp (
>
> output empty,
>
> ..
>
> input data_in,
>
> input pop);
>
> mp_data_in : assume property (@ (posedge clk) *fslave_if_mp*.data_in
> !=32'h00000000);
>
> // Legal to use modports in interfaces?
>
> *endinterface* : fifo_if
>
>
> According to a vendor that I brought this forward, he is saying* that it
> is still up for debate if the reference to the modport should be legal or
> not. *
>
> Some tools seem to ignore the modport so the behavior will be the same with
> or without the modport in the code.
>
>
>
> Question for this sv-ac committee: What does, or should, the LRM say? We
> need clarification on this. Using the modport allows a user to write
> better assumptions knowing what is input or output.
>
>
> --------------------------------------------------------------------------
> Ben Cohen (831) 345-1759
> http://www.systemverilog.us/ ben@systemverilog.us <mailto:
> ben@systemverilog.us>
> * SystemVerilog Assertions Handbook, 2nd Edition, 2010 ISBN
> 878-0-9705394-8-7
> * A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
> * Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004,
> ISBN 0-9705394-6-0
> * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
> 0-9705394-2-8
> * Component Design by Example, 2001 ISBN 0-9705394-0-1
> * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN
> 0-7923-8474-1
> * VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
> --------------------------------------------------------------------------
>
>
>
>
>
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