[sv-ac] RE: checker question

Hi Manisha,

This is a known issue and we need to fix it in this PAR. See Mantis 2809.

Regards,
Dmitry

-----Original Message-----
From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of Kulshrestha, Manisha
Sent: Friday, March 18, 2011 12:56
To: sv-ac@eda.org
Subject: [sv-ac] checker question

Hi Dimitry,

In section 17.5 it says:

An always procedure in a checker body may contain deferred and concurrent assertions, nonblocking variable
assignments (see 17.7.1) and a procedural timing control statement using an event control. All other
statements shall not appear inside an always procedure.

But in a previous example (17.3.2) there is a checker instance inside always procedure in a checker. Is this legal ?

checker c3(event clk, logic a);
p3: assert property (@clk a);
endchecker
checker c2(event clk, logic a);
c3 c3_stat(clk, a);
always @(clk) begin
c3 c3_proc(clk, a); // ILLEGAL if c2 is instantiated as below
end
endchecker
module m2(logic clk, logic [3:0] d);
always @(posedge clk) begin
for (int i = 0; i < 4; i++) begin
c2 check_loop(posedge clk, d [const'(i)]);
end
end
endmodule : m2

We may need a fix in the LRM to make it clear.

Thanks.
Manisha

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