[sv-ac] couple of errors in the assumption proposal
Subject: [sv-ac] couple of errors in the assumption proposal
From: Surrendra Dudani (Surrendra.Dudani@synopsys.com)
Date: Mon Sep 22 2003 - 08:45:37 PDT
First error is in the example for Section 1.2.4 of the 3.1a
proposal
property proto
@(posedge clk) (req dist {0:=40, 1:=60})
|-> req[*1:$] ##0 ack;
endproperty
property proto_assertion
@(posedge clk) (req inside {0, 1})
|-> req[*1:$] ##0 ack;
endproperty
Should be written as
a1: assume property @(posedge clk)
req dist {0:=40, 1:=60} ;
property proto
@(posedge clk) req |->
req[*1:$] ##0 ack;
endproperty
a1_assertion: assert property req inside {0, 1} ;
property proto_assertion
@(posedge clk) req
|-> req[*1:$] ##0 ack;
endproperty
Second error is a typo is in the example of Section 1.3.3
req_v dist {0:=40, 1:=60};
Should be
v_req dist {0:=40, 1:=60};
Surrendra
**********************************************
Surrendra A. Dudani
Synopsys, Inc.
377 Simarano Drive, Suite 300
Marlboro, MA 01752
Tel: 508-263-8072
Fax: 508-263-8123
email: Surrendra.Dudani@synopsys.com
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: Mon Sep 22 2003 - 08:46:22 PDT