[sv-ac] 3.1a proposals

Subject: [sv-ac] 3.1a proposals
From: Surrendra Dudani (Surrendra.Dudani@synopsys.com)
Date: Mon Sep 15 2003 - 13:49:09 PDT

Attached are the proposals for the following enhancement items:

1. assume directive for concurrent assertion to be used as environment, random test generation constraint
3.  alignment/ synchronization with testbench constraints language, clarify on usage/application differences
5. non-blocking clocked assignment variables to be assigned within assertion block
6. Message reporting using assertion values, debug sampled variable assignments
9. Allow passing of infinite range as argument to properties and sequences, consider possibility of alternate syntax for infinite
14. enhance gated clock support, extend past functionality to allow conditional evaluation of number of clock cycles

Surrendra


 




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Surrendra A. Dudani
Synopsys, Inc.
377 Simarano Drive, Suite 300
Marlboro, MA 01752

Tel:   508-263-8072
Fax:   508-263-8123
email: Surrendra.Dudani@synopsys.com 
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