Subject: Re: [sv-ac] Query on assertion BNF
From: Kausik Datta (kausikd@cal.interrasystems.com)
Date: Sun Sep 07 2003 - 21:37:23 PDT
Hi John,
Thanks for the clarification.
Do you have any plan to add atleast one example like this in the next
version of System Verilog LRM?
Thanks
Kausik
John Havlicek wrote:
>##1 ##2 a
>
>is equivalent to
>
>##3 a
>
>J.H.
>
>>Date: Thu, 04 Sep 2003 10:11:14 +0530
>>From: Kausik Datta<kausikd@cal.interrasystems.com>
>>Reply-To: kausikd@interrasystems.com
>>Organization: Interra Systems India Pvt. Ltd.
>>X-Accept-Language: en-us
>>Sender: owner-sv-ac@eda.org
>>Precedence: bulk
>>
>>Hi,
>>I am new in this mailing list.
>>We are using System Verilog 3.1 assertion.
>>But in the LRM of SV 3.1 the sequence_expr is as follows
>>
>>sequence_expr ::= cycle_delay_range sequence_expr {cycle_delay_range
>>sequence_expr}
>>
>>Does this mean
>>##1 ##2 a
>>is also a valid sequence_expr ?
>>If so what will be the semantic of this expression?
>>Thanks
>>Kausik
>>
>
>
This archive was generated by hypermail 2b28 : Sun Sep 07 2003 - 21:40:50 PDT